ANNEXE 4 : LISTING DES PROGRAMMES
4.1 Le fichier Top
######################## top.vhd
##############################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
port (
clk : IN STD_LOGIC; CLK commun aux 2 modules
I/O module reconfigurable
cen : IN STD_LOGIC;
clr : IN STD_LOGIC;
s_cpt : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
I/O module system à ppc405
sys_clk : in std_logic;
HALTNEG : in std_logic;
System_reset : in std_logic;
Leds : inout std_logic_vector(0 to 7);
rx : in std_logic;
tx : out std_logic;
sram_addr : out std_logic_vector(0 to 31);
sram_data : inout std_logic_vector(0 to 31);
sram_cen : out std_logic_vector(0 to 0);
sram_oen : out std_logic_vector(0 to 0);
sram_wen : out std_logic;
sram_ben : out std_logic_vector(0 to 3);
sram_rst : out std_logic;
sram_cefn : out std_logic
);
end top;
architecture STRUCTURE of top is
Internal signal du CLK commun
SIGNAL clk_in : STD_LOGIC;
|
Internal signals du module reconfigurable
SIGNAL cpt_clk_sig : STD_LOGIC; --clk
SIGNAL clr_sig : STD_LOGIC;
SIGNAL cen_sig : STD_LOGIC;
SIGNAL s_cpt_sig : STD_LOGIC_VECTOR (7 DOWNTO 0);
Internal signals du module ppc
signal HALTNEG_IBUF : std_logic;
signal sys_clk_sig : std_logic;
|
|
signal
|
leds_I
|
: std_logic_vector(0 to
|
7);
|
|
signal
|
leds_O
|
: std_logic_vector(0 to
|
7);
|
|
signal
|
leds_T
|
: std_logic_vector(0 to
|
7);
|
|
signal
|
rx_IBUF
|
: std_logic;
|
|
|
signal
|
sram_addr_OBUF
|
: std_logic_vector(0 to
|
31);
|
|
signal
|
sram_ben_OBUF
|
: std_logic_vector(0 to
|
3);
|
|
signal
|
sram_cefn_OBUF
|
: std_logic;
|
|
|
signal
|
sram_cen_OBUF
|
: std_logic_vector(0 to
|
0);
|
|
signal
|
sram_data_I
|
: std_logic_vector(0 to
|
31);
|
|
signal
|
sram_data_O
|
: std_logic_vector(0 to
|
31);
|
|
signal
|
sram_data_T
|
: std_logic_vector(0 to
|
31);
|
|
signal
|
sram_oen_OBUF
|
: std_logic_vector(0 to
|
0);
|
|
signal
|
sram_rst_OBUF
|
: std_logic;
|
|
|
signal
|
sram_wen_OBUF
|
: std_logic;
|
|
|
signal
|
system_reset_IBUF
|
: std_logic;
|
|
signal tx_OBUF : std_logic;
ATTRIBUTE BOX_TYPE : STRING;
-IIIIIIIIIIIIIIIIIIII composant system
IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
component system is
port (
sys_clk : in std_logic;
HALTNEG : in std_logic;
system_reset : in std_logic;
rx : in std_logic;
tx : out std_logic;
sram_addr : out std_logic_vector(0 to 31);
sram_cen : out std_logic_vector(0 to 0);
sram_oen : out std_logic_vector(0 to 0);
sram_wen : out std_logic;
sram_ben : out std_logic_vector(0 to 3);
sram_rst : out std_logic;
sram_cefn : out std_logic;
leds_I : in std_logic_vector(0 to 7);
leds_O : out std_logic_vector(0 to 7);
leds_T : out std_logic_vector(0 to 7);
sram_data_I : in std_logic_vector(0 to 31);
sram_data_O : out std_logic_vector(0 to 31);
sram_data_T : out std_logic_vector(0 to 31)
);
end component;
ATTRIBUTE BOX_TYPE OF system : COMPONENT IS "BLACK_BOX";
-IIIIIIIIIIIIIIIIIIIIIIII COMPONENT compteur
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
component compteur is
Port (
s_cpt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
cen : IN STD_LOGIC;
clr : IN STD_LOGIC
);
end component;
ATTRIBUTE BOX_TYPE OF compteur : COMPONENT IS "BLACK_BOX";
IIII Buffer Clk BUFG : Peut-on utiliser BUFGP? BUFG marche
IIIIIIIIII component BUFG is
port (
I : in std_logic;
O : out std_logic
);
end component;
ATTRIBUTE BOX_TYPE OF BUFG : COMPONENT IS "BLACK_BOX";
--IIIIIIIIIIIIIIIIII Buffer d'entree IBUF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII component IBUF is
port (
I : in std_logic;
O : out std_logic
);
end component;
ATTRIBUTE BOX_TYPE OF IBUF : COMPONENT IS "BLACK_BOX";
IIIIIIIIII Buffer d'entre/sortie tri-states IOBUF
IIIIIIIIIIIIIIIIIIIIIIIIII component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
ATTRIBUTE BOX_TYPE OF IOBUF : COMPONENT IS "BLACK_BOX";
-----IIIIIIIIIIII Buffer de sortie OBUF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII component OBUF is
port (
I : in std_logic;
O : out std_logic
);
end component;
ATTRIBUTE BOX_TYPE OF OBUF: COMPONENT IS "BLACK_BOX";
----IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII BEGIN TOP
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Begin
----IIIIIIIIII Instanciation du module reconfigurable COMPTEUR
et
connexions aux signaux internes
count : compteur PORT MAP (
clk => sys_clk_sig,
cen => cen_sig,
clr => clr_sig,
s_cpt => s_cpt_sig);
----IIIIII instanciation des Buffers I/Os et...
---- ...connexions des signaux internes du module cOMPTEUR
clr_buf : IBUF PORT MAP (I=>clr, O=>clr_sig);
cen_buf : IBUF PORT MAP (I=>cen, O=>cen_sig);
loop_buf1: for i in 0 to 7 generate
s_cpt_buf : OBUF PORT MAP (I=>s_cpt_sig(i),
O=>s_cpt(i));
end generate;
----IIIIII Instanciation du module fixe SYSTEM et ...
connexions aux signaux internes
ppc_subsystem : system
port map (
sys_clk => sys_clk_sig,
HALTNEG => HALTNEG_IBUF,
system_reset => system_reset_IBUF,
rx => rx_IBUF,
tx => tx_OBUF,
sram_addr => sram_addr_OBUF,
sram_cen => sram_cen_OBUF(0 to 0),
sram_oen => sram_oen_OBUF(0 to 0),
sram_wen => sram_wen_OBUF,
sram_ben => sram_ben_OBUF,
sram_rst => sram_rst_OBUF,
sram_cefn => sram_cefn_OBUF,
leds_I => leds_I,
leds_O => leds_O,
leds_T => leds_T,
sram_data_I => sram_data_I,
sram_data_O => sram_data_O,
sram_data_T => sram_data_T
);
IIIIII Distribution du CLK aux 2 modules
ibuf_0 : IBUF port map ( I => clk, O => clk_in );
bufgp_0 : BUFG port map ( I => clk_in , O => sys_clk_sig
);
End CLK Distribution
----### instanciation des Buffers I/Os et...
---- ...connexions des signaux internes du module SYSTEM
ibuf_1 : IBUF port map ( I => HALTNEG, O => HALTNEG_IBUF
);
ibuf_2 : IBUF port map ( I => system_reset, O =>
system_reset_IBUF );
buffer sortie inout leds
loop_leds_iobuf : for i in 0 to 7 generate leds_iobuf : IOBUF
port map ( I=>leds_O(i), IO=>leds(i), O => leds_I(i), T
=> leds_T(i) );
end generate ;
buffer sortie inout sram
loop_sram_data_iobuf : for i in 0 to 31 generate
sram_data_iobuf : IOBUF
port map ( I=>sram_data_O(i), IO=>sram_data(i),
O => sram_data_I(i), T => sram_data_T(i) );
end generate ;
ibuf_11 : IBUF port map (I => rx, O => rx_IBUF );
obuf_12 : OBUF port map (I => tx_OBUF, O => tx );
obuf_13 : OBUF port map (I => sram_addr_OBUF(0), O =>
sram_addr(0) );
obuf_14 : OBUF port map (I => sram_addr_OBUF(1), O =>
sram_addr(1));
obuf_15 : OBUF port map (I => sram_addr_OBUF(2),O =>
sram_addr(2));
obuf_16 : OBUF port map (I => sram_addr_OBUF(3), O =>
sram_addr(3));
obuf_17 : OBUF port map (I => sram_addr_OBUF(4), O =>
sram_addr(4));
obuf_18 : OBUF port map (I => sram_addr_OBUF(5), O =>
sram_addr(5) );
obuf_19 : OBUF port map (I => sram_addr_OBUF(6), O =>
sram_addr(6) );
obuf_20 : OBUF port map ( I => sram_addr_OBUF(7), O =>
sram_addr(7));
obuf_21 : OBUF port map ( I => sram_addr_OBUF(8), O =>
sram_addr(8) );
obuf_22 : OBUF port map ( I => sram_addr_OBUF(9), O =>
sram_addr(9) );
obuf_23 : OBUF port map ( I => sram_addr_OBUF(10), O =>
sram_addr(10) );
obuf_24 : OBUF port map ( I => sram_addr_OBUF(11), O =>
sram_addr(11) );
obuf_25 : OBUF port map ( I => sram_addr_OBUF(12), O =>
sram_addr(12) );
obuf_26 : OBUF port map ( I => sram_addr_OBUF(13), O =>
sram_addr(13) );
obuf_27 : OBUF port map ( I => sram_addr_OBUF(14), O =>
sram_addr(14) );
obuf_28 : OBUF port map ( I => sram_addr_OBUF(15), O =>
sram_addr(15) );
obuf_29 : OBUF port map ( I => sram_addr_OBUF(16), O =>
sram_addr(16) );
obuf_30 : OBUF port map ( I => sram_addr_OBUF(17), O =>
sram_addr(17) );
obuf_31 : OBUF port map ( I => sram_addr_OBUF(18), O =>
sram_addr(18) );
obuf_32 : OBUF port map ( I => sram_addr_OBUF(19), O =>
sram_addr(19) );
obuf_33 : OBUF port map ( I => sram_addr_OBUF(20), O =>
sram_addr(20) );
obuf_34 : OBUF port map ( I => sram_addr_OBUF(21), O =>
sram_addr(21) );
obuf_35 : OBUF port map ( I => sram_addr_OBUF(22), O =>
sram_addr(22) );
obuf_36 : OBUF port map ( I => sram_addr_OBUF(23), O =>
sram_addr(23) );
obuf_37 : OBUF port map ( I => sram_addr_OBUF(24), O =>
sram_addr(24) );
obuf_38 : OBUF port map ( I => sram_addr_OBUF(25), O =>
sram_addr(25));
obuf_39 : OBUF port map ( I => sram_addr_OBUF(26), O =>
sram_addr(26) );
obuf_40 : OBUF port map ( I => sram_addr_OBUF(27), O =>
sram_addr(27) );
obuf_41 : OBUF port map (I => sram_addr_OBUF(28), O =>
sram_addr(28) );
obuf_42 : OBUF port map ( I => sram_addr_OBUF(29), O =>
sram_addr(29) );
obuf_43 : OBUF port map ( I => sram_addr_OBUF(30), O =>
sram_addr(30) );
obuf_44 : OBUF port map ( I => sram_addr_OBUF(31), O =>
sram_addr(31) );
obuf_77 : OBUF port map ( I => sram_cen_OBUF(0), O =>
sram_cen(0) );
obuf_78 : OBUF port map ( I => sram_oen_OBUF(0), O =>
sram_oen(0) );
obuf_79 : OBUF port map ( I => sram_wen_OBUF, O => sram_wen
);
obuf_80 : OBUF port map ( I => sram_ben_OBUF(0), O =>
sram_ben(0) );
obuf_81 : OBUF port map ( I => sram_ben_OBUF(1), O =>
sram_ben(1) );
obuf_82 : OBUF port map ( I => sram_ben_OBUF(2), O =>
sram_ben(2) );
obuf_83 : OBUF port map ( I => sram_ben_OBUF(3), O =>
sram_ben(3) );
obuf_84 : OBUF port map ( I => sram_rst_OBUF, O => sram_rst
);
obuf_104 : OBUF port map ( I => sram_cefn_OBUF, O =>
sram_cefn );
end architecture STRUCTURE;
4.2 Code VHDL d'un design du module reconfigurable
################### compteur_lent.vhd
########################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compteur is Port (
s_cpt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
cen : IN STD_LOGIC;
clr : IN STD_LOGIC
);
end compteur;
architecture compt_lent of compteur is
SIGNAL cpt: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL clk_1h : STD_LOGIC; -- horloge 1 hertz
SIGNAL X : STD_LOGIC_VECTOR (24 DOWNTO 0);
CONSTANT N : INTEGER:= 24999999 ; --- modulo 50 000 000
Begin
proc_div: process (clk,clr,cen, X)
begin
if clr='0' -- push1
then X<="0000000000000000000000000"; elsif cen='1' then
if clk'event and clk='1'then
if X>N then X<="0000000000000000000000000";
else X<=X+1;
end if;
end if ;
if X>12499999 then -- rapport cyclique 1/2
clk_1h<='1';
else clk_1h<='0';
end if;
end if;
end process;
proc_cpt : process (clk_1h,clr,cen)
begin
if clr='0' then cpt<="00000000";
elsif cen='1' then
if clk_1h'event and clk_1h='1'then cpt<=cpt+1;
end if;
end if;
end process;
s_cpt<=not cpt;
end compt_lent;
4.3 Fichier de contraintes
################### top.ucf
########################
#####Constraints For Virtex II - Pro Design
# Timing Ignore Constraints #
# Non-critical Reset Nets
# Level Interrupt from Uart
# Non-critical Nets
# Clock Period Constraints #
# 100 MHz Ref Clk to DCM Produces PLB(1X), CPU(FX=3X) #
(Over-Constrain Period by 250 ps to allow for Jitter,
# Skew, Noise, Etc)
# Multicycle Path Constraints for DCR #
# IO Pad Location Constraints (2VP4/7 AFX Board)
# CLK commun aux deux modules -#
NET "clk" PERIOD = 10.00;
NET "clk" LOC = "v12" ;
##### module reconfigurable count situé à gauche,
instance "count"####
NET "cen" LOC = "W5" | PULLUP ; # PUSH2 NET "clr" LOC = "V7" |
PULLUP ; # PUSH1
# sorties compteur 8 bits, module de gauche;
NET "s_cpt<0>" LOC = "W6" ; # LED2 DS8
NET "s_cpt<1>" LOC = "V8" ; # LED1 DS7
NET "s_cpt<2>" LOC = "D5" ; # LCD Data Bit 2 D2 sur main
board
NET "s_cpt<3>" LOC = "D6" ; # LCD Data Bit 3 D3 sur main
board
NET "s_cpt<4>" LOC = "C7" ; # LCD Data Bit 4 D4 sur main
board
NET "s_cpt<5>" LOC = "D8" ; # LCD Data Bit 5 D5 sur main
board
NET "s_cpt<6>" LOC = "C8" ; # LCD Data Bit 6 D6 sur main
board
NET "s_cpt<7>" LOC = "E8" ; # LCD Data Bit 7 D7 sur main
board
#NET "clk_out" LOC = "D7" ; # LCD Data Bit 0 D0 sur main board
##### module SYSTEM situé à droite, instance
"ppc_subsystem" ##### #PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "system_reset" LOC = "v15" ;
##### UART
NET "tx" LOC = "E14" ;
NET "rx" LOC = "F14" ;
###### ETHERNET
NET "HALTNEG" LOC = "AA11" | PULLUP ;
NET "leds<0>" LOC = "u10" ;
NET "leds<1>" LOC = "v10" ;
NET "leds<2>" LOC = "W13" | PULLUP ;
NET "leds<3>" LOC = "Y13" | PULLUP ;
NET "leds<4>" LOC = "W14" | PULLUP ;
NET "leds<5>" LOC = "W15" | PULLUP ;
NET "leds<6>" LOC = "Y15" | PULLUP ;
NET "leds<7>" LOC = "W16" | PULLUP ;
#### Connexion a la SRAM externe de la carte d'extension P160
Comm
NET "sram_addr<0>" LOC = "u11" ;
NET "sram_addr<10>" LOC = "J22" ;
NET "sram_addr<11>" LOC = "P20" ;
NET "sram_addr<12>" LOC = "N20" ;
NET "sram_addr<13>" LOC = "L17" ;
NET "sram_addr<14>" LOC = "J17" ;
NET "sram_addr<15>" LOC = "P22" ;
NET "sram_addr<16>" LOC = "L21" ;
NET "sram_addr<17>" LOC = "K22" ;
NET "sram_addr<18>" LOC = "J18" ;
NET "sram_addr<19>" LOC = "K17" ;
NET "sram_addr<1>" LOC = "d18" ;
NET "sram_addr<20>" LOC = "K21" ;
NET "sram_addr<21>" LOC = "J21" ;
NET "sram_addr<22>" LOC = "AB21" ;
NET "sram_addr<23>" LOC = "U18" ;
NET "sram_addr<24>" LOC = "T18" ;
NET "sram_addr<25>" LOC = "P17" ;
NET "sram_addr<26>" LOC = "N19" ;
NET "sram_addr<27>" LOC = "R18" ;
NET "sram_addr<28>" LOC = "P18" ;
NET "sram_addr<29>" LOC = "N18" ;
NET "sram_addr<2>" LOC = "d17" ;
NET "sram_addr<30>" LOC = "w18" ;
NET "sram_addr<31>" LOC = "v11" ;
NET "sram_addr<3>" LOC = "BANK1" ;
NET "sram_addr<4>" LOC = "BANK4" ;
NET "sram_addr<5>" LOC = "BANK4" ;
NET "sram_addr<6>" LOC = "u14" ;
NET "sram_addr<7>" LOC = "v14" ;
NET "sram_addr<8>" LOC = "u13" ;
NET "sram_addr<9>" LOC = "v13" ;
NET "sram_ben<0>" LOC = "F20" ;
NET "sram_ben<1>" LOC = "G19" ;
NET "sram_ben<2>" LOC = "1" ;
NET "sram_ben<3>" LOC = "2" ;
NET "sram_cefn" LOC = "L20" ;
NET "sram_cen<0>" LOC = "Y22" ;
NET "sram_data<0>" LOC = "L19" ;
NET "sram_data<10>" LOC = "T19" ;
NET "sram_data<11>" LOC = "M18" ;
NET "sram_data<12>" LOC = "U20" ;
NET "sram_data<13>" LOC = "M19" ;
NET "sram_data<14>" LOC = "N17" ;
NET "sram_data<15>" LOC = "M20" ;
NET "sram_data<16>" LOC = "R22" ;
NET "sram_data<17>" LOC = "J20" ;
NET "sram_data<18>" LOC = "J19" ;
NET "sram_data<19>" LOC = "T22" ;
NET "sram_data<1>" LOC = "L18" ;
NET "sram_data<20>" LOC = "U21" ;
NET "sram_data<21>" LOC = "K20" ;
NET "sram_data<22>" LOC = "V22" ;
NET "sram_data<23>" LOC = "K18" ;
NET "sram_data<24>" LOC = "R21" ;
NET "sram_data<25>" LOC = "P21" ;
NET "sram_data<26>" LOC = "U22" ;
NET "sram_data<27>" LOC = "T21" ;
NET "sram_data<28>" LOC = "K19" ;
NET "sram_data<29>" LOC = "V21" ;
NET "sram_data<2>" LOC = "R19" ;
NET "sram_data<30>" LOC = "Y21" ;
NET "sram_data<31>" LOC = "W22" ;
NET "sram_data<3>" LOC = "T20" ;
NET "sram_data<4>" LOC = "U19" ;
NET "sram_data<5>" LOC = "V20" ;
NET "sram_data<6>" LOC = "M17" ;
NET "sram_data<7>" LOC = "V19" ;
NET "sram_data<8>" LOC = "R20" ;
NET "sram_data<9>" LOC = "AA22" ;
NET "sram_oen<0>" LOC = "W21" ;
NET "sram_rst" LOC = "E13" ;
NET "sram_wen" LOC = "H18" ;
IIIIIIIIIIIIIIIIPACE: Start of PACE Area Constraints
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIII module de gauche, reconfigurable
AREA_GROUP "AG_count" RANGE = SLICE_X0Y79:SLICE_X15Y0 ;
AREA_GROUP "AG_count" MODE = RECONFIG ;
INST count AREA_GROUP = AG_count ;
######## Module de droite, systeme a processeur
AREA_GROUP "AG_ppc_subsystem" RANGE = SLICE_X16Y79:SLICE_X67Y0
;
AREA_GROUP "AG_ppc_subsystem" MODE = RECONFIG ;
INST ppc_subsystem AREA_GROUP = AG_ppc_subsystem ;
#PACE: End of Constraints generated by PACE
4.4 Les codes sources des programmes
développés en C pour le processeur PPC
/***************************** Include Files
*********************************/ #include <xstatus.h>
#include <xbasic_types.h>
#include <xparameters.h>
#include <xhwicap_i.h>
#include <xuartlite_l.h>
#include <string.h>
#include "xuartlite.h"
unsigned int* xfert_rbt_file(unsigned int*, int ); // fonction de
xfert de fichier RBT en SRAM int read_frame_icap(void); // fonction de lecture
des frames par ICAP
int write_frame_icap(unsigned int** , unsigned int *);
void write_frame(void);
void init_icap(void);
void intro(void);
#define NBRE_MAX_CONFIG_FILE 10 /* Nombre maximum de modules
bitstreams à
charger en SRAM */
#define ADDR_DEBUT_CONFIG 0x81000000 // adresse de debut SRAM
unsigned char nom_fichier[NBRE_MAX_CONFIG_FILE][35]; // tableau noms
fichiers
unsigned int nbr_lignes[NBRE_MAX_CONFIG_FILE]; // tableau taille
des configurations
XHwIcap MyIcap;
main()
{
int r, i, l;
int nbre_config;
unsigned int* config_pt[NBRE_MAX_CONFIG_FILE]; /* pointeur des
configurations en
mémoire SRAM */
unsigned int taille_config =0;
Xuint8 Ch, caract;
r=0;
config_pt[0] = (unsigned int*)ADDR_DEBUT_CONFIG; // donc unsigned
int** config_pt;
intro ();
xil_printf("\n\r\n\r Entrez un nombre de Modules a charger <
10 ");
Ch=XUartLite_RecvByte ( XPAR_MYUART_BASEADDR ); xil_printf("
%c\n\r", Ch);
nbre_config=atoi(&Ch);
// Transfert des fichiers RBT en mémoire SRAM
while (r<nbre_config) {
xil_printf("\n\r Transfert fichier RBT %d..", r+1);
/* config_pt[r+1] = pointeur sur la prochaine configuration,
retournée par la fonction unsigned int*
xfert_rbt_file(unsigned int*, int ) */
config_pt[r+1]=xfert_rbt_file(config_pt[r], r);
/* xil_printf("\n\r&Debut: %x --> %x &Fin : %x -->
%x " , config_pt[r], *(config_pt[r]), config_pt[r+1]-1,
*(config_pt[r+1]-1)); */
/* xil_printf(" &Fin : %x --> %x " , config_pt[r+1]-1,
*(config_pt[r+1]-1)); */
// xil_printf("\n\rr=%d adresse debut config: %x\n\r" ,r+2 ,
config_pt[r+1]);
// taille_config=config_pt[r];
// xil_printf("\n\r Nom Design %d : %s" ,r+1, nom_fichier[r]
);
// xil_printf("\n\r Taille(mots 32 bits) : %d \n\r
",nbr_lignes[r]);
r++;
} // END while (r<nbre_config)
/*
// Affichage des adresses SRAM et Noms fichiers pour
vérification
for(r=0; r<nbre_config; r++ )
{
xil_printf("\n\r Nom fichier RBT %d --> %s Taille -->
%d\n\r " ,r+1, nom_fichier[r], nbr_lignes[r]); xil_printf("\n\r Configuration
%d & debut: %x Contenu %x ",r+1, config_pt[r],*(config_pt[r]));
xil_printf("\n\r Configuration %d & fin : %x Contenu %x
",r+1, config_pt[r+1]-1, *(config_pt[r+1]-1));
// for(i=0; i<config_pt[r+1]-config_pt[r]; i++)
// xil_printf( "\n\rSRAM & %x = %x ", config_pt[r]+i,
*(config_pt[r]+i));
}
*/
init_icap();
// write_frame();
// xil_printf("\n\r\n\r Dans main(): Taille=%d Config_pt[0]=
%x",nbr_lignes[0], config_pt[0]);
// l=read_frame_icap();
// l=write_frame_icap( config_pt[0], nbr_lignes );
// l=write_frame_icap( config_pt, nbr_lignes );
// A chaque fois, l pourra etre utilisé pour controle
d'erreur
xil_printf("\n\r Choix du Module a charger:");
while(1) {
for (i=0;i<r;i++) xil_printf("\n\r%s tapez --> %d
",nom_fichier[i], i+1 ); caract=XUartLite_RecvByte ( XPAR_MYUART_BASEADDR );
// xil_printf(" \n\r caract= %c", caract);
l=atoi(&caract);
// xil_printf("\n\r l= %d ",l);
if((l<1)||(l>=r))
xil_printf(" \n\r Erreur tapez le bon chiffre");
else {
xil_printf(" %d", l);
l=write_frame_icap( config_pt+l-1, nbr_lignes+l-1 ); // l pourra
etre utilisé pour controle d'erreur
xil_printf("\n\r\n\r Fin Reconfiguration %s ",
nom_fichier[l-1]);
}
}
while(1);
} // fin main
/********************* Constant Definitions for
ICAP ***********************/
#define ICAP_BUFFER_SIZE 512 /* Nombre de mots du bitstream
à envoyer ds le buffer_bram
d'ICAP, sachant que sa taille maxi est 4 Ko, soit 512 mots de 32
bits maxi *\
#define XHI_EX_MY_ID 0 /* IdCode de l'instance ICAP donné
par l'utilisateur, n'a rien a voir avec
l'IdCode constructeur */
#define XHI_EX_MAX_RETRIES 100
#define XHI_EX_ONE_WORD 1
#define XHI_EX_ADDRESS_OFFSET 0
/***********************END Constant Definitions for ICAP
***********************/
/* Implements the Assert callback function defined by
xbasic_types.h.
* It potentially enters an infinite loop depending on the value
of the XWaitInAssert variable.
* @param File is the name of the filename of the source (indique
nom du fichier du code en cours d'execution * @param Line is the linenumber
within File (indique la ligne d'erreur dans le code)
**************************************************************************/
void XHwIcap_AssertHandler (char* FilenamePtr, int LineNumber)
{
//xil_printf("\n\rAssert occured in file: %s at line %d
\n\r",FilenamePtr,LineNumber);
return;
}
void init_icap(void)
{
// Xuint32 IdCode;
// Holds status of XHwIcap calls.
XStatus Status;
// Instance of HwIcap
// XHwIcap MyIcap;
XAssertCallback MyCallBack;
// Setup assert handler.
MyCallBack = &XHwIcap_AssertHandler;
XAssertSetCallback(MyCallBack);
Status = XHwIcap_Initialize( &MyIcap, XHI_EX_MY_ID,XHI_XVP7);
// added by me if (Status != XST_SUCCESS) {
// xil_printf("\n\r Failed to initialize: %d \n\r",Status);
exit(-1);
}
else xil_printf("\n\r Succeed to initialize Icap: %d
\n\r",Status);
}
/*********** FUNCTION RECONFIGURER UN MODULE VIA L'ICAP
***************/
int write_frame_icap( unsigned int** config_pt, unsigned int
*taille)
{
/* Instance of HwIcap */
int *t;
unsigned int icap_buffer_size;
// unsigned int reste;
unsigned int cpt_mot; // pour parcourir tous les mots de
configuration en partant du pointeur // sur le debut de configuration
*t=*taille;
// xil_printf("\n\r Beginning Module Reconfiguration");
cpt_mot=0;
while (*t>0){
for (icap_buffer_size=0;
icap_buffer_size<ICAP_BUFFER_SIZE;icap_buffer_size++)
{
XHwIcap_StorageBufferWrite(&MyIcap, icap_buffer_size,
*(*config_pt+cpt_mot)); // BRAM icap
/* xil_printf( "\n\r__trace *t=%d icap_buffer_size = %d compteur
mot = %d", *t,
icap_buffer_size, cpt_mot); */
cpt_mot++;
}
// xil_printf( "\n\r Test de *t= %d ", *t );
if (*t<ICAP_BUFFER_SIZE) /* si le reste de mots a
écrire est inférieur a la taille du
buffer...évite d'aller au-delà de la fin des mots
de configuration du module */
{
XHwIcap_DeviceWrite(&MyIcap, XHI_EX_ADDRESS_OFFSET,*t);
/* if((*taille-*t)%10==0) xil_printf( "\n\r__trace
*(*config_pt+*taille-*t) = & %x *t= %d ",
*(*config_pt+*taille-*t),*t);
// xil_printf( "\n\r__trace Ecriture ICAP %d valeurs", *t); */
}
else
{ XHwIcap_DeviceWrite(&MyIcap,
XHI_EX_ADDRESS_OFFSET,ICAP_BUFFER_SIZE);
/* xil_printf( "\n\r__trace Ecriture ICAP %d valeurs",
ICAP_BUFFER_SIZE);
* /
}
(*t)-=ICAP_BUFFER_SIZE;
} //END while (*t)
/* xil_printf( "\n\r__SRAM & %x --> %x icap_buffer_size=
%d",
*config_pt+*taille-*t,
*(*config_pt+*taille-*t),icap_buffer_size); */
// xil_printf("\n\r Fin Reconfiguration Module");
return 0;
} /********** END FUNCTION Reconfiguration d'un Module
*******/
/********** FUNCTION CHARGEANT LES FICHIERS RBT EN
MEMOIRE *******/ /********** SRAM VIA HYPERTERMINAL ET PORT SERIE
****************/ unsigned int* xfert_rbt_file(unsigned int* config_pt, int
r)
{
unsigned char reception=0;
int i=0; // pour parcourir tout le fichier
int j=0;
int ligne=0;
int ligne_temp=0;
int l=0;
unsigned int data=0;
// int r=0;
unsigned int* tab_data ; // bitstream en mémoire
unsigned int nbr_lignes_temp;
unsigned int taille_bits;
unsigned int p=0;
int q=0;
int k=0; // pour chercher fin de lignes et tabulations...
int m=0; int n=0; // int nbr_lignes=0;
unsigned char tab_char[250]; // tableau pour stocker
l'entête du fichier RBT
// unsigned char nom_fichier[20];
unsigned char nbr_bits[8];
// xil_printf("\n\r\n\r_transferez votre fichier RBT:\n\r\n\r
");
// Analyse des 7 lignes d'entête du fichier RBT, de ligne 0
à 6 while(ligne<7)
{
reception=XUartLite_RecvByte ( XPAR_MYUART_BASEADDR );
tab_char[i]=reception;
i++;
// 10= saut ligne; 13= retour chariot; 9= tabulation, // Comptage
des lignes
if (reception==10) ligne++;
/* à la fin de ce while() on a parcouru toute
l'entête du fichier RBT , ligne =7 */
}
ligne_temp=ligne; // ligne vaut 7 ici
// xil_printf("\n\r_ valeur de ligne fin entête: %d \r\n\r
", ligne);
/*
xil_printf("\n\r Transfert en cours ");
xil_printf("\n\r Analyse entete fichier RBT ");*/
for ( k=0; k<i-1; k++) { /* parcours tableau entete tab_char[]
*/
/* Recherche nom du fichier dans tableau - entête et
stockage dans tableau nom_fichier[30] */
if ((tab_char[k]==9)&(j==0))
/* j=0 pour la 1ère tabulation(9) dans entête */
{
while(tab_char[k+1]!=13)
{ /* fin ligne 1ère tabulation */
k++;
nom_fichier[r][n]=tab_char[k]; n++;
j=n;
/* surveiller de près l'utilisation de j ailleurs, peut
perturber le programme */
}
nom_fichier[r][n]='\0'; /* pour boucler la chaîne
nom_fichier */
// xil_printf("\n\r \n\r");
// xil_printf("\n\r Nom Design Config %d: %s",r+1,
nom_fichier[r]);
}
/* Recherche nombre de bits dans tableau-entete et stockage dans
tableau nbr_bits[20] */
if (tab_char[k]==10) /* lignes */
{
ligne_temp--;
/* avant décrémentation, ligne=7, à la fin
ligne=1 => 7ème ligne */
}
if ((tab_char[k]==9)&&(ligne_temp==1)) /* tabulation de
la 7ème ligne */
{
n=0;
while (tab_char[k+1]!=13)
{
k++;
nbr_bits[n]=tab_char[k];
j++;
n++;
}
nbr_bits[n]='\0'; /* pour boucler la chaîne nombre de bits
*/
taille_bits=atoi(&(nbr_bits[0]));
}
} /* Fin boucle for (k=0; k<i-1; k++) de parcours du tableau
entête*/
tab_data=config_pt; // on affecte à tab_data le pointeur
sur config reçu en argument l=0; p=0; data=0;
nbr_lignes[r]=taille_bits/32; // calcul de la taille de
tab_data
/* xil_printf("\n\r Fin Analyse entête fichier RBT ");
xil_printf("\n\r Nom Design Config %d: %s",r+1,
nom_fichier[r]);
xil_printf("\n\r Taille du Design %d (mots 32 bits) = %d \n\r
",r+1,nbr_lignes[r]); */
nbr_lignes_temp=taille_bits/32;
n=nbr_lignes_temp/10;
while(nbr_lignes_temp)
{
reception=XUartLite_RecvByte ( XPAR_MYUART_BASEADDR ); if
((reception=='0')||(reception=='1')) {
data = 2*data + (unsigned int)reception-(unsigned int)48; }
// Sinon atteinte fin de ligne
else if((int)reception==13) {
*(tab_data+p)=data;
}
else if(reception==10) {
// if(ligne%300==0) xil_printf("\r\n %d --> %x", ligne,
*(tab_data+p));
if((ligne-7)%n==0) xil_printf("%d%c..", 10*ligne/n,'%'
);
ligne++;
p++;
nbr_lignes_temp-- ; data=0; //
}
} // Fin while(nbr_lignes_temp)
/* xil_printf("\n\r taille_bits =%d Nombre de lignes = %d",
taille_bits, nbr_lignes_temp); */
/* xil_printf("\r\n derniere ligne:%d & %x --> mot
%x\n\r", ligne-1,tab_data+p-1, *(tab_data+p-1)); */
return (tab_data+p); //
retourne le pointeur sur la configuration suivante
} /******* END FUNCTION ************/
/************** FUNCTION INTRO_ACCUEIL
*********************/
void intro( )
{
char Ch;
xil_printf("\n\r"); xil_printf("\n\r"); xil_printf("\n\r");
xil_printf("\n\r"); xil_printf("\n\r");
xil_printf("\n\r******************************************************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r********** STAGE ETIS_ARCHI 2005 *************");
xil_printf("\n\r************ by G. Wassi
****************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r");
xil_printf("\n\r******************************************************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r***********
******************");
xil_printf("\n\r*********** SELF RECONFIGURING
******************");
xil_printf("\n\r*********** PLATFORM DEMO
******************");
xil_printf("\n\r***********
******************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r******************************************************");
xil_printf("\n\r");
xil_printf("APPUYEZ UNE TOUCHE POUR CONTINUER "); Ch=inbyte();
} /***************** END FUNCTION INTRO_ACCUEIL ************/
################### Linker script
#####################
// $xilinx_legal_disclaimer */
_STACK_SIZE = 1k;
MEMORY { extmem : ORIGIN = 0x81000000, LENGTH = 1M
}
STARTUP(boot.o)
ENTRY(_boot)
GROUP(libxil.a libc.a)
| 
